module SOC(
    input wire clk,
    input wire rst,
    input wire ex_Rd,
    input wire [9:0]ex_Addr,
    output [15:0] ioOut
);

wire [31:0] pc;
wire [31:0] inst;
wire romCe;

wire memCe;
wire memWr;    
wire [31:0] memAddr;
wire [31:0] rdData;
wire [31:0] wtData;

wire [31:0] ramRdData;
wire [31:0] ioRdData;
wire ramCe;
wire ramWe;
wire [31:0] ramAddr;
wire [31:0] ramWtData;
wire ioCe;
wire ioWe;
wire [31:0] ioAddr;
wire [31:0] ioWtData;


MIOC mioc0(
.memCe(memCe),
.memWr(memWr),
.memAddr(memAddr),
.wtData(wtData),
.ramRdData(ramRdData),
.ioRdData(ioRdData),
.rdData(rdData),
.ramCe(ramCe),
.ramWe(ramWe),
.ramAddr(ramAddr),
.ramWtData(ramWtData),
.ioCe(ioCe),
.ioWe(ioWe),
.ioAddr(ioAddr),
.ioWtData(ioWtData)
);


DATAMEM datamem0(       
.clk(clk),
.ce(ramCe),
.we(ramWe),
.addr(ramAddr),
.dataIn(ramWtData),
.dataOut(ramRdData)
);


IO io0(
.ce(ioCe),
.ioWr(ioWe),
.clk(clk),
.ex_Rd(ex_Rd),
.ex_Addr(ex_Addr),
.wtData(ioWtData),
.Addr(ioAddr),
.rdData(ioRdData),
.ioOut(ioOut)
);




MIPS mips0(
.clk(clk),
.rst(rst),
.inst(inst),
.rdData(rdData),
.romCe(romCe),
.pc(pc),
.wtData(wtData),
.memAddr(memAddr),
.memCe(memCe),
.memWr(memWr)
);

INSTMEM instmem0(
    .ce(romCe),
    .addr(pc),
    .data(inst)
);

endmodule

